Verilog Top Errors

This is a list of the most common Verilog errors. The top five account forabout 50% of all errors.
The Top 5 Verilog Errors:
1)The left hand side of a procedural assignment not declared as a register.
2)Missing or mismatched begin-end statements.
3)Missing base ('b) for binary numbers (this means the compiler considers themto be decimal numbers).
4)Using the wrong apostrophe in compiler directives (should be the backwardsapostrophe, or grave accent, `) and number bases (should be the normalapostrophe, or inverted comma, ').
5)Missing semicolon at the end of a statement.
Other Common Errors:
1)Trying to define task and function arguments in brackets after the name of thetask or function.
2)Forgetting to instance the module under test in a test fixture.
3)Using a procedural continuous assignment instead of a continuousassignment (i.e. ‘assign’ in the wrong place).
4)Trying to use reserved words as identifiers (e.g. xor).
5)No timing controls in an always (causes it to loop indefinitely).
6)Using a logical or operator ( ) instead of the reserved word or in an eventcontrol (E.g. @(a or b) ).
7)Using implicit wires for connections to vector ports.
8)Connecting ports in the wrong order in a module instance.
9)Incorrect bracketing (placement of begin-end) in nested if-else statements.
10)Using the wrong form of ‘equals’. ‘=’ is used in assignments; ‘==’ is used when comparing numerical values; ‘===’ is used to match an exact sequenceof 0s, 1s, Xs and Zs.
@ Seen from Verilog VHDL Golden Reference Guide.Copy Righted by the Author of the Book. @